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| author | CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> | 2025-05-20 07:18:51 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-06-01 06:38:53 -0400 |
| commit | a8d178e1492a1a803898501a84829ac517ae2fb0 (patch) | |
| tree | aa28bf8d0114b97bdbe8ca113aef55575e449f49 | |
| parent | 0f178860df3489a9d3c19a5f7f024e6aa6c26515 (diff) | |
| download | qemu-a8d178e1492a1a803898501a84829ac517ae2fb0.zip qemu-a8d178e1492a1a803898501a84829ac517ae2fb0.tar.gz qemu-a8d178e1492a1a803898501a84829ac517ae2fb0.tar.bz2 | |
pcie: Add helper to declare PASID capability for a pcie device
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
Message-Id: <20250520071823.764266-2-clement.mathieu--drif@eviden.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/pci/pcie.c | 25 | ||||
| -rw-r--r-- | include/hw/pci/pcie.h | 6 | ||||
| -rw-r--r-- | include/hw/pci/pcie_regs.h | 5 |
3 files changed, 35 insertions, 1 deletions
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 1b12db6..4f935ff 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1214,3 +1214,28 @@ void pcie_acs_reset(PCIDevice *dev) pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); } } + +/* PASID */ +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod) +{ + static const uint16_t control_reg_rw_mask = 0x07; + uint16_t capability_reg; + + assert(pasid_width <= PCI_EXT_CAP_PASID_MAX_WIDTH); + + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, + PCI_EXT_CAP_PASID_SIZEOF); + + capability_reg = ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIFT; + capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0; + capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0; + pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg); + + /* Everything is disabled by default */ + pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0); + + pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask); + + dev->exp.pasid_cap = offset; +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 70a5de0..fe82e0a 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -70,8 +70,9 @@ struct PCIExpressDevice { uint16_t aer_cap; PCIEAERLog aer_log; - /* Offset of ATS capability in config space */ + /* Offset of ATS and PASID capabilities in config space */ uint16_t ats_cap; + uint16_t pasid_cap; /* ACS */ uint16_t acs_cap; @@ -150,4 +151,7 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); + +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod); #endif /* QEMU_PCIE_H */ diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 9d3b686..4d9cf4a 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -86,6 +86,11 @@ typedef enum PCIExpLinkWidth { #define PCI_ARI_VER 1 #define PCI_ARI_SIZEOF 8 +/* PASID */ +#define PCI_PASID_VER 1 +#define PCI_EXT_CAP_PASID_MAX_WIDTH 20 +#define PCI_PASID_CAP_WIDTH_SHIFT 8 + /* AER */ #define PCI_ERR_VER 2 #define PCI_ERR_SIZEOF 0x48 |