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authorRichard Henderson <richard.henderson@linaro.org>2021-04-19 13:22:27 -0700
committerPeter Maydell <peter.maydell@linaro.org>2021-04-30 11:16:49 +0100
commita736cbc303f3c3f79b7b0b09e0dd4e18c8bcf94c (patch)
treee8f330c7cd92565a53f8eed1cee225db0a14678d
parent33e74c3172defc841692b4281d2dbd8f8a966e17 (diff)
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target/arm: Fix decode of align in VLDST_single
The encoding of size = 2 and size = 3 had the incorrect decode for align, overlapping the stride field. This error was hidden by what should have been unnecessary masking in translate. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210419202257.161730-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/neon-ls.decode4
-rw-r--r--target/arm/translate-neon.c.inc4
2 files changed, 4 insertions, 4 deletions
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index c17f501..0a2a0e1 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
vd=%vd_dp size=0 stride=1
-VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
vd=%vd_dp size=1 stride=%imm1_5_p1
-VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
vd=%vd_dp size=2 stride=%imm1_6_p1
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index f6c68e3..0e58287 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -606,7 +606,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
switch (nregs) {
case 1:
if (((a->align & (1 << a->size)) != 0) ||
- (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+ (a->size == 2 && (a->align == 1 || a->align == 2))) {
return false;
}
break;
@@ -621,7 +621,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
}
break;
case 4:
- if ((a->size == 2) && ((a->align & 3) == 3)) {
+ if (a->size == 2 && a->align == 3) {
return false;
}
break;