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| author | Manos Pitsidianakis <manos.pitsidianakis@linaro.org> | 2024-12-11 14:44:38 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-12-17 15:17:46 +0000 |
| commit | a65a24b9cfcff5bb132386fc78ab87c0019d396c (patch) | |
| tree | 264e63695244cedc26c1c68bf2d946f3d4943667 | |
| parent | 4278186a3045d14723b9445a45ee9bca0fd023f4 (diff) | |
| download | qemu-a65a24b9cfcff5bb132386fc78ab87c0019d396c.zip qemu-a65a24b9cfcff5bb132386fc78ab87c0019d396c.tar.gz qemu-a65a24b9cfcff5bb132386fc78ab87c0019d396c.tar.bz2 | |
target/arm: Add decodetree entry for DSB nXS variant
The DSB nXS variant is always both a reads and writes request type.
Ignore the domain field like we do in plain DSB and perform a full
system barrier operation.
The DSB nXS variant is part of FEAT_XS made mandatory from Armv8.7.
Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211144440.2700268-5-peter.maydell@linaro.org
[PMM: added missing "UNDEF unless feature present" check]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/a64.decode | 3 | ||||
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 9 |
2 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 7aa10f5..8c798cd 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -260,6 +260,9 @@ WFIT 1101 0101 0000 0011 0001 0000 001 rd:5 CLREX 1101 0101 0000 0011 0011 ---- 010 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 +# For the DSB nXS variant, types always equals MBReqTypes_All and we ignore the +# domain bits. +DSB_nXS 1101 0101 0000 0011 0011 -- 10 001 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111 SB 1101 0101 0000 0011 0011 0000 111 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ecbc46b..7c65fc3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1986,6 +1986,15 @@ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a) return true; } +static bool trans_DSB_nXS(DisasContext *s, arg_DSB_nXS *a) +{ + if (!dc_isar_feature(aa64_xs, s)) { + return false; + } + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + return true; +} + static bool trans_ISB(DisasContext *s, arg_ISB *a) { /* |