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| author | Paolo Bonzini <pbonzini@redhat.com> | 2018-01-09 13:45:14 -0200 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-01-17 23:04:31 -0200 |
| commit | a33a2cfe2f771b360b3422f6cdf566a560860bfc (patch) | |
| tree | 5845a91308870630711d35cd581523dddf314f53 | |
| parent | 807e9869b8c4119b81df902625af818519e01759 (diff) | |
| download | qemu-a33a2cfe2f771b360b3422f6cdf566a560860bfc.zip qemu-a33a2cfe2f771b360b3422f6cdf566a560860bfc.tar.gz qemu-a33a2cfe2f771b360b3422f6cdf566a560860bfc.tar.bz2 | |
i386: Add support for SPEC_CTRL MSR
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20180109154519.25634-3-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| -rw-r--r-- | target/i386/cpu.h | 3 | ||||
| -rw-r--r-- | target/i386/kvm.c | 14 | ||||
| -rw-r--r-- | target/i386/machine.c | 20 |
3 files changed, 37 insertions, 0 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f64e5ed..10264b2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -353,6 +353,7 @@ typedef enum X86Seg { #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b +#define MSR_IA32_SPEC_CTRL 0x48 #define MSR_IA32_TSCDEADLINE 0x6e0 #define FEATURE_CONTROL_LOCKED (1<<0) @@ -1125,6 +1126,8 @@ typedef struct CPUX86State { uint32_t pkru; + uint64_t spec_ctrl; + /* End of state preserved by INIT (dummy marker). */ struct {} end_init_save; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 4912f4d..ad4b159 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -91,6 +91,7 @@ static bool has_msr_hv_synic; static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_xss; +static bool has_msr_spec_ctrl; static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -1153,6 +1154,9 @@ static int kvm_get_supported_msrs(KVMState *s) case HV_X64_MSR_TSC_FREQUENCY: has_msr_hv_frequencies = true; break; + case MSR_IA32_SPEC_CTRL: + has_msr_spec_ctrl = true; + break; } } } @@ -1635,6 +1639,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); + } #ifdef TARGET_X86_64 if (lm_capable_kernel) { kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); @@ -1643,6 +1650,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); } #endif + /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates. @@ -1980,6 +1988,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_xss) { kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); } + if (has_msr_spec_ctrl) { + kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); + } if (!env->tsc_valid) { @@ -2327,6 +2338,9 @@ static int kvm_get_msrs(X86CPU *cpu) env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; } break; + case MSR_IA32_SPEC_CTRL: + env->spec_ctrl = msrs[i].data; + break; } } diff --git a/target/i386/machine.c b/target/i386/machine.c index df5ec35..361c05a 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -818,6 +818,25 @@ static const VMStateDescription vmstate_mcg_ext_ctl = { } }; +static bool spec_ctrl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return env->spec_ctrl != 0; +} + +static const VMStateDescription vmstate_spec_ctrl = { + .name = "cpu/spec_ctrl", + .version_id = 1, + .minimum_version_id = 1, + .needed = spec_ctrl_needed, + .fields = (VMStateField[]){ + VMSTATE_UINT64(env.spec_ctrl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -936,6 +955,7 @@ VMStateDescription vmstate_x86_cpu = { #ifdef TARGET_X86_64 &vmstate_pkru, #endif + &vmstate_spec_ctrl, &vmstate_mcg_ext_ctl, NULL } |