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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-02-27 11:33:20 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-03-06 14:08:11 +0000 |
| commit | a1ad913da0cb85239309cae93b7a1bf83ad3e1e5 (patch) | |
| tree | 8c5e3f39b8c4db0e893f908dfbb08db3479d0bb0 | |
| parent | f214bdde5a65ac24626a63040ca899b6860c0ed6 (diff) | |
| download | qemu-a1ad913da0cb85239309cae93b7a1bf83ad3e1e5.zip qemu-a1ad913da0cb85239309cae93b7a1bf83ad3e1e5.tar.gz qemu-a1ad913da0cb85239309cae93b7a1bf83ad3e1e5.tar.bz2 | |
target/arm: Simplify register counting in arm_gen_dynamic_svereg_xml
Rather than increment base_reg and num, compute num from the change
to base_reg at the end. Clean up some nearby comments.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/gdbstub64.c | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 811833d..070ba20 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -277,32 +277,35 @@ static void output_vector_union_type(GString *s, int reg_width) g_string_append(s, "</union>"); } -int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) +int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) { ARMCPU *cpu = ARM_CPU(cs); GString *s = g_string_new(NULL); DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml; - int i, reg_width = (cpu->sve_max_vq * 128); - info->num = 0; + int reg_width = cpu->sve_max_vq * 128; + int base_reg = orig_base_reg; + int i; + g_string_printf(s, "<?xml version=\"1.0\"?>"); g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"); g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">"); + /* Create the vector union type. */ output_vector_union_type(s, reg_width); - /* Finally the sve prefix type */ + /* Create the predicate vector type. */ g_string_append_printf(s, "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>", reg_width / 8); - /* Then define each register in parts for each vq */ + /* Define the vector registers. */ for (i = 0; i < 32; i++) { g_string_append_printf(s, "<reg name=\"z%d\" bitsize=\"%d\"" " regnum=\"%d\" type=\"svev\"/>", i, reg_width, base_reg++); - info->num++; } + /* fpscr & status registers */ g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\"" " regnum=\"%d\" group=\"float\"" @@ -310,27 +313,29 @@ int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg) g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\"" " regnum=\"%d\" group=\"float\"" " type=\"int\"/>", base_reg++); - info->num += 2; + /* Define the predicate registers. */ for (i = 0; i < 16; i++) { g_string_append_printf(s, "<reg name=\"p%d\" bitsize=\"%d\"" " regnum=\"%d\" type=\"svep\"/>", i, cpu->sve_max_vq * 16, base_reg++); - info->num++; } g_string_append_printf(s, "<reg name=\"ffr\" bitsize=\"%d\"" " regnum=\"%d\" group=\"vector\"" " type=\"svep\"/>", cpu->sve_max_vq * 16, base_reg++); + + /* Define the vector length pseudo-register. */ g_string_append_printf(s, "<reg name=\"vg\" bitsize=\"64\"" " regnum=\"%d\" type=\"int\"/>", base_reg++); - info->num += 2; + g_string_append_printf(s, "</feature>"); - info->desc = g_string_free(s, false); + info->desc = g_string_free(s, false); + info->num = base_reg - orig_base_reg; return info->num; } |