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| author | Peter Maydell <peter.maydell@linaro.org> | 2024-01-09 14:43:52 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-09 14:43:52 +0000 |
| commit | a13cd25d9bb1e972a25f4002d0465f3d9b05c5aa (patch) | |
| tree | 468ed06965a9089648d11265c6e27d905941be43 | |
| parent | 1274a47fbd9739b628835936dbefa0294d9dd32c (diff) | |
| download | qemu-a13cd25d9bb1e972a25f4002d0465f3d9b05c5aa.zip qemu-a13cd25d9bb1e972a25f4002d0465f3d9b05c5aa.tar.gz qemu-a13cd25d9bb1e972a25f4002d0465f3d9b05c5aa.tar.bz2 | |
target/arm: Handle HCR_EL2 accesses for FEAT_NV2 bits
FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the
feature is enabled, allow this bit to be written in HCR_EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Miguel Luis <miguel.luis@oracle.com>
| -rw-r--r-- | target/arm/cpu-features.h | 5 | ||||
| -rw-r--r-- | target/arm/helper.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 3a43c32..7a590c8 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -844,6 +844,11 @@ static inline bool isar_feature_aa64_nv(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0; } +static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >= 2; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && diff --git a/target/arm/helper.c b/target/arm/helper.c index 24751e0..e3e5653 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5857,6 +5857,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_nv, cpu)) { valid_mask |= HCR_NV | HCR_NV1 | HCR_AT; } + if (cpu_isar_feature(aa64_nv2, cpu)) { + valid_mask |= HCR_NV2; + } } if (cpu_isar_feature(any_evt, cpu)) { |