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authorRichard Henderson <richard.henderson@linaro.org>2023-06-21 12:27:27 +0200
committerRichard Henderson <richard.henderson@linaro.org>2023-06-26 17:33:00 +0200
commita0eaae08c7c6a59c185cf646b02f4167b2ac6ec0 (patch)
tree06257b623f9014b19f62525cea3a5f4aa168412d
parent187ba6945345cedf2f343fcc33e5616186aebe9d (diff)
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accel/tcg: Renumber TLB_DISCARD_WRITE
Move to fill a hole in the set of bits. Reduce the total number of tlb bits by 1. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--include/exec/cpu-all.h4
-rw-r--r--tcg/tcg-op-ldst.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index b561861..8018ce7 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
+/* Set if TLB entry writes ignored. */
+#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
-/* Set if TLB entry writes ignored. */
-#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
/*
* Use this mask to check interception with an alignment mask
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index a4f51bf..0fcc161 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -39,7 +39,7 @@ static void check_max_alignment(unsigned a_bits)
* The requested alignment cannot overlap the TLB flags.
* FIXME: Must keep the count up-to-date with "exec/cpu-all.h".
*/
- tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits);
+ tcg_debug_assert(a_bits + 5 <= tcg_ctx->page_bits);
#endif
}