diff options
| author | Michael Tokarev <mjt@tls.msk.ru> | 2024-11-26 16:12:09 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-11-26 16:12:09 +0000 |
| commit | a0dfe58acda236ebb4ebf292b1c5980487d6d046 (patch) | |
| tree | 0730dd5748696114b2339817391c459737667135 | |
| parent | ba54a7e6b86884e43bed2d2f5a79c719059652a8 (diff) | |
| download | qemu-a0dfe58acda236ebb4ebf292b1c5980487d6d046.zip qemu-a0dfe58acda236ebb4ebf292b1c5980487d6d046.tar.gz qemu-a0dfe58acda236ebb4ebf292b1c5980487d6d046.tar.bz2 | |
target/arm/tcg/cpu32.c: swap ATCM and BTCM register names
According to Cortex-R5 r1p2 manual, register with opcode2=0 is
BTCM and with opcode2=1 is ATCM, - exactly the opposite from how
qemu labels them. Just swap the labels to avoid confusion, -
both registers are implemented as always-zero.
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241121171602.3273252-1-mjt@tls.msk.ru
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/cpu32.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 20c2737..2a77701 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -574,9 +574,9 @@ static void cortex_a15_initfn(Object *obj) static const ARMCPRegInfo cortexr5_cp_reginfo[] = { /* Dummy the TCM region regs for the moment */ - { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, + { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST }, - { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, + { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_CONST }, { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, |