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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-14 10:13:21 -0500 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-05-19 12:15:47 -0500 |
| commit | 9f55e5a947512fdf8f2c4f8ccdfa84efaac8960c (patch) | |
| tree | 6de30ca1aacf3d99418a56b0d9fd4388a9113c25 | |
| parent | a6f62100a8eb0092f613d974142d3789522530f4 (diff) | |
| download | qemu-9f55e5a947512fdf8f2c4f8ccdfa84efaac8960c.zip qemu-9f55e5a947512fdf8f2c4f8ccdfa84efaac8960c.tar.gz qemu-9f55e5a947512fdf8f2c4f8ccdfa84efaac8960c.tar.bz2 | |
target/i386: Add stub generator for helper_set_dr
This removes an ifdef from the middle of disas_insn,
and ensures that the branch is not reachable.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20210514151342.384376-30-richard.henderson@linaro.org>
| -rw-r--r-- | target/i386/tcg/translate.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5c321b3..28eb0e8 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -179,6 +179,19 @@ typedef struct DisasContext { #define REX_B(S) 0 #endif +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { qemu_build_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(set_dr, TCGv_env env, TCGv_i32 reg, TCGv val) +#endif + static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); @@ -8075,7 +8088,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x121: /* mov reg, drN */ case 0x123: /* mov drN, reg */ if (check_cpl0(s)) { -#ifndef CONFIG_USER_ONLY modrm = x86_ldub_code(env, s); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of @@ -8104,7 +8116,6 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32); gen_op_mov_reg_v(s, ot, rm, s->T0); } -#endif /* !CONFIG_USER_ONLY */ } break; case 0x106: /* clts */ |