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author | Richard Henderson <richard.henderson@linaro.org> | 2021-07-16 08:17:18 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-07-21 07:45:38 -1000 |
commit | 9ef0c6d6a7d81992a2326416a9ce12eef2824861 (patch) | |
tree | dc4c99d93f6823e1cca48772a23cd8926bce3ee8 | |
parent | 47345e7124709d280f14551113a20fd81ad2bf20 (diff) | |
download | qemu-9ef0c6d6a7d81992a2326416a9ce12eef2824861.zip qemu-9ef0c6d6a7d81992a2326416a9ce12eef2824861.tar.gz qemu-9ef0c6d6a7d81992a2326416a9ce12eef2824861.tar.bz2 |
qemu/atomic: Add aligned_{int64,uint64}_t types
Use it to avoid some clang-12 -Watomic-alignment errors,
forcing some structures to be aligned and as a pointer when
we have ensured that the address is aligned.
Tested-by: Cole Robinson <crobinso@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r-- | accel/tcg/atomic_template.h | 4 | ||||
-rw-r--r-- | include/qemu/atomic.h | 14 | ||||
-rw-r--r-- | include/qemu/stats64.h | 2 | ||||
-rw-r--r-- | linux-user/hppa/cpu_loop.c | 2 | ||||
-rw-r--r-- | softmmu/timers-state.h | 2 | ||||
-rw-r--r-- | util/qsp.c | 4 |
6 files changed, 20 insertions, 8 deletions
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index afa8a9d..d347462 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -28,8 +28,8 @@ # define SHIFT 4 #elif DATA_SIZE == 8 # define SUFFIX q -# define DATA_TYPE uint64_t -# define SDATA_TYPE int64_t +# define DATA_TYPE aligned_uint64_t +# define SDATA_TYPE aligned_int64_t # define BSWAP bswap64 # define SHIFT 3 #elif DATA_SIZE == 4 diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index fe5467d..112a299 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -271,7 +271,19 @@ _oldn; \ }) -/* Abstractions to access atomically (i.e. "once") i64/u64 variables */ +/* + * Abstractions to access atomically (i.e. "once") i64/u64 variables. + * + * The i386 abi is odd in that by default members are only aligned to + * 4 bytes, which means that 8-byte types can wind up mis-aligned. + * Clang will then warn about this, and emit a call into libatomic. + * + * Use of these types in structures when they will be used with atomic + * operations can avoid this. + */ +typedef int64_t aligned_int64_t __attribute__((aligned(8))); +typedef uint64_t aligned_uint64_t __attribute__((aligned(8))); + #ifdef CONFIG_ATOMIC64 /* Use __nocheck because sizeof(void *) might be < sizeof(u64) */ #define qatomic_read_i64(P) \ diff --git a/include/qemu/stats64.h b/include/qemu/stats64.h index fdd3d1b..8024022 100644 --- a/include/qemu/stats64.h +++ b/include/qemu/stats64.h @@ -21,7 +21,7 @@ typedef struct Stat64 { #ifdef CONFIG_ATOMIC64 - uint64_t value; + aligned_uint64_t value; #else uint32_t low, high; uint32_t lock; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 3aaaf33..82d8183 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -82,7 +82,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) o64 = *(uint64_t *)g2h(cs, old); n64 = *(uint64_t *)g2h(cs, new); #ifdef CONFIG_ATOMIC64 - r64 = qatomic_cmpxchg__nocheck((uint64_t *)g2h(cs, addr), + r64 = qatomic_cmpxchg__nocheck((aligned_uint64_t *)g2h(cs, addr), o64, n64); ret = r64 != o64; #else diff --git a/softmmu/timers-state.h b/softmmu/timers-state.h index 8c262ce..94bb739 100644 --- a/softmmu/timers-state.h +++ b/softmmu/timers-state.h @@ -47,7 +47,7 @@ typedef struct TimersState { int64_t last_delta; /* Compensate for varying guest execution speed. */ - int64_t qemu_icount_bias; + aligned_int64_t qemu_icount_bias; int64_t vm_clock_warp_start; int64_t cpu_clock_offset; @@ -83,8 +83,8 @@ typedef struct QSPCallSite QSPCallSite; struct QSPEntry { void *thread_ptr; const QSPCallSite *callsite; - uint64_t n_acqs; - uint64_t ns; + aligned_uint64_t n_acqs; + aligned_uint64_t ns; unsigned int n_objs; /* count of coalesced objs; only used for reporting */ }; typedef struct QSPEntry QSPEntry; |