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| author | Richard Henderson <rth@twiddle.net> | 2017-07-27 13:26:33 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-09-07 11:57:35 -0700 |
| commit | 95ede84f4de18747d03d79c148013cff99acd60b (patch) | |
| tree | 124701bda22bd2a0c5c8a12f34456d55d92bacb1 | |
| parent | 647ab96aaf5defeb138e48d610f7f633c587b40d (diff) | |
| download | qemu-95ede84f4de18747d03d79c148013cff99acd60b.zip qemu-95ede84f4de18747d03d79c148013cff99acd60b.tar.gz qemu-95ede84f4de18747d03d79c148013cff99acd60b.tar.bz2 | |
tcg/arm: Tighten tlb indexing offset test
We are not going to use ldrd for loading the comparator
for 32-bit guests, so don't limit cmp_off to 8 bits then.
This eliminates one insn in the tlb load for some guests.
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | tcg/arm/tcg-target.inc.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index 66c369c..6c12b16 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1202,7 +1202,9 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, } /* We checked that the offset is contained within 16 bits above. */ - if (add_off > 0xfff || (use_armv6_instructions && cmp_off > 0xff)) { + if (add_off > 0xfff + || (use_armv6_instructions && TARGET_LONG_BITS == 64 + && cmp_off > 0xff)) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, (24 << 7) | (cmp_off >> 8)); base = TCG_REG_R2; |