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| author | Paolo Bonzini <pbonzini@redhat.com> | 2024-06-20 11:07:39 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-06-28 14:44:52 +0200 |
| commit | 944f4001346019a3cd05567695aa48830c904626 (patch) | |
| tree | 5313ced23c6300d42cd865ef8639b7da892bbe6c | |
| parent | e36b976da4f6f4c0d434e6bb811f60b7b445e8ea (diff) | |
| download | qemu-944f4001346019a3cd05567695aa48830c904626.zip qemu-944f4001346019a3cd05567695aa48830c904626.tar.gz qemu-944f4001346019a3cd05567695aa48830c904626.tar.bz2 | |
target/i386: use cpu_cc_dst for CC_OP_POPCNT
It is the only CCOp, among those that compute ZF from one of the cc_op_*
registers, that uses cpu_cc_src. Do not make it the odd one off,
instead use cpu_cc_dst like the others.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/i386/cpu.h | 2 | ||||
| -rw-r--r-- | target/i386/tcg/cc_helper.c | 2 | ||||
| -rw-r--r-- | target/i386/tcg/emit.c.inc | 4 | ||||
| -rw-r--r-- | target/i386/tcg/translate.c | 4 |
4 files changed, 6 insertions, 6 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 52571ab..1b4edbe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1332,7 +1332,7 @@ typedef enum { CC_OP_BMILGQ, CC_OP_CLR, /* Z set, all other flags clear. */ - CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */ + CC_OP_POPCNT, /* Z via CC_DST, all other flags clear. */ CC_OP_NB, } CCOp; diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index f76e9cb..301ed95 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -107,7 +107,7 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1, case CC_OP_CLR: return CC_Z | CC_P; case CC_OP_POPCNT: - return src1 ? 0 : CC_Z; + return dst ? 0 : CC_Z; case CC_OP_MULB: return compute_all_mulb(dst, src1); diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 11faa70..fc74778 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -2804,10 +2804,10 @@ static void gen_POPA(DisasContext *s, X86DecodedInsn *decode) static void gen_POPCNT(DisasContext *s, X86DecodedInsn *decode) { - decode->cc_src = tcg_temp_new(); + decode->cc_dst = tcg_temp_new(); decode->cc_op = CC_OP_POPCNT; - tcg_gen_mov_tl(decode->cc_src, s->T0); + tcg_gen_mov_tl(decode->cc_dst, s->T0); tcg_gen_ctpop_tl(s->T0, s->T0); } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ad18198..eb353dc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -324,7 +324,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = { [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2, [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, [CC_OP_CLR] = 0, - [CC_OP_POPCNT] = USES_CC_SRC, + [CC_OP_POPCNT] = USES_CC_DST, }; static void set_cc_op_1(DisasContext *s, CCOp op, bool dirty) @@ -1020,7 +1020,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) case CC_OP_CLR: return (CCPrepare) { .cond = TCG_COND_ALWAYS }; case CC_OP_POPCNT: - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src }; + return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst }; default: { MemOp size = (s->cc_op - CC_OP_ADDB) & 3; |