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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-10-24 07:50:20 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-10-24 07:51:37 +0100 |
| commit | 93f379b0c43617b1361f742f261479eaed4959cb (patch) | |
| tree | 820b8f48c523040b54c6501a35d8f83308f4df01 | |
| parent | f478847f1ee0df9397f561025ab2f687fd923571 (diff) | |
| download | qemu-93f379b0c43617b1361f742f261479eaed4959cb.zip qemu-93f379b0c43617b1361f742f261479eaed4959cb.tar.gz qemu-93f379b0c43617b1361f742f261479eaed4959cb.tar.bz2 | |
target/arm: Only flush tlb if ASID changes
Since QEMU does not implement ASIDs, changes to the ASID must flush the
tlb. However, if the ASID does not change there is no reason to flush.
In testing a boot of the Ubuntu installer to the first menu, this reduces
the number of flushes by 30%, or nearly 600k instances.
Reviewed-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20181019015617.22583-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 1486ff7..0ea95b0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2758,12 +2758,10 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* 64 bit accesses to the TTBRs can change the ASID and so we - * must flush the TLB. - */ - if (cpreg_field_is_64bit(ri)) { + /* If the ASID changes (with a 64-bit write), we must flush the TLB. */ + if (cpreg_field_is_64bit(ri) && + extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { ARMCPU *cpu = arm_env_get_cpu(env); - tlb_flush(CPU(cpu)); } raw_write(env, ri, value); |