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| author | Aurelien Jarno <aurelien@aurel32.net> | 2017-07-02 21:31:25 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2017-07-18 23:39:15 +0200 |
| commit | 92f1f83e34f0454b98f3a7fc082636c38cafa115 (patch) | |
| tree | 4a54a2a81365da17d8b5c1bbe2f5b7ce4e51284a | |
| parent | 82e8251374568ba63343b695925c883a7da3db6f (diff) | |
| download | qemu-92f1f83e34f0454b98f3a7fc082636c38cafa115.zip qemu-92f1f83e34f0454b98f3a7fc082636c38cafa115.tar.gz qemu-92f1f83e34f0454b98f3a7fc082636c38cafa115.tar.bz2 | |
target/sh4: return result of fcmp using TCG
Since that the T bit of the SR register is mapped using a TGC global,
it's better to return the value through TCG than writing it directly. It
allows to declare the helpers with the flag TCG_CALL_NO_WG.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170702202814.27793-5-aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target/sh4/helper.h | 8 | ||||
| -rw-r--r-- | target/sh4/op_helper.c | 16 | ||||
| -rw-r--r-- | target/sh4/translate.c | 10 |
3 files changed, 18 insertions, 16 deletions
diff --git a/target/sh4/helper.h b/target/sh4/helper.h index d239892..767a6d5 100644 --- a/target/sh4/helper.h +++ b/target/sh4/helper.h @@ -21,10 +21,10 @@ DEF_HELPER_FLAGS_3(fadd_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(fcnvsd_FT_DT, TCG_CALL_NO_WG, f64, env, f32) DEF_HELPER_FLAGS_2(fcnvds_DT_FT, TCG_CALL_NO_WG, f32, env, f64) -DEF_HELPER_3(fcmp_eq_FT, void, env, f32, f32) -DEF_HELPER_3(fcmp_eq_DT, void, env, f64, f64) -DEF_HELPER_3(fcmp_gt_FT, void, env, f32, f32) -DEF_HELPER_3(fcmp_gt_DT, void, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmp_eq_FT, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmp_eq_DT, TCG_CALL_NO_WG, i32, env, f64, f64) +DEF_HELPER_FLAGS_3(fcmp_gt_FT, TCG_CALL_NO_WG, i32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmp_gt_DT, TCG_CALL_NO_WG, i32, env, f64, f64) DEF_HELPER_FLAGS_3(fdiv_FT, TCG_CALL_NO_WG, f32, env, f32, f32) DEF_HELPER_FLAGS_3(fdiv_DT, TCG_CALL_NO_WG, f64, env, f64, f64) DEF_HELPER_FLAGS_2(float_FT, TCG_CALL_NO_WG, f32, env, i32) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 64206cf..c3d19b1 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -268,44 +268,44 @@ float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1) return t0; } -void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) +uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) { int relation; set_float_exception_flags(0, &env->fp_status); relation = float32_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t = (relation == float_relation_equal); + return relation == float_relation_equal; } -void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) +uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) { int relation; set_float_exception_flags(0, &env->fp_status); relation = float64_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t = (relation == float_relation_equal); + return relation == float_relation_equal; } -void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) +uint32_t helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1) { int relation; set_float_exception_flags(0, &env->fp_status); relation = float32_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t = (relation == float_relation_greater); + return relation == float_relation_greater; } -void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) +uint32_t helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1) { int relation; set_float_exception_flags(0, &env->fp_status); relation = float64_compare(t0, t1, &env->fp_status); update_fpscr(env, GETPC()); - env->sr_t = (relation == float_relation_greater); + return relation == float_relation_greater; } float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9360522..4c3512f 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1077,10 +1077,10 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_DT(cpu_env, fp0, fp1); + gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_DT(cpu_env, fp0, fp1); + gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); return; } gen_store_fpr64(fp0, DREG(B11_8)); @@ -1109,11 +1109,13 @@ static void _decode_opc(DisasContext * ctx) cpu_fregs[FREG(B7_4)]); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_FT(cpu_env, cpu_fregs[FREG(B11_8)], + gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env, + cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_FT(cpu_env, cpu_fregs[FREG(B11_8)], + gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env, + cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); return; } |