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authorRob Bradford <rbradford@rivosinc.com>2024-01-23 11:10:28 +0000
committerAlistair Francis <alistair.francis@wdc.com>2024-02-09 20:43:14 +1000
commit8caeda5bf5ba73b080a79ca09203372a94d36e49 (patch)
treebb7826751f52fdd5ed8e3ad8a446ec2c302e5d53
parent5fb20f76008e13f99ec42867f4ebd4089b71ba96 (diff)
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target/riscv: Add Zaamo and Zalrsc extension infrastructure
These extensions represent the atomic operations from A (Zaamo) and the Load-Reserved/Store-Conditional operations from A (Zalrsc) Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240123111030.15074-2-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/cpu_cfg.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index e241922..833bf58 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -78,7 +78,9 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_zdinx;
+ bool ext_zaamo;
bool ext_zacas;
+ bool ext_zalrsc;
bool ext_zawrs;
bool ext_zfa;
bool ext_zfbfmin;