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| author | Stefan Weil <sw@weilnetz.de> | 2023-04-09 22:18:28 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-04-24 22:56:55 -0400 |
| commit | 8a9ede6f511c5a028e1c1fc949a97ff30c36bebe (patch) | |
| tree | 5b8b46a70b4164dacf8dc60e889e669d186b3629 | |
| parent | 2b6fc0b859a1b8a5bc2a48c56e8cb595748b7c3f (diff) | |
| download | qemu-8a9ede6f511c5a028e1c1fc949a97ff30c36bebe.zip qemu-8a9ede6f511c5a028e1c1fc949a97ff30c36bebe.tar.gz qemu-8a9ede6f511c5a028e1c1fc949a97ff30c36bebe.tar.bz2 | |
docs/cxl: Fix sentence
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20230409201828.1159568-1-sw@weilnetz.de>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | docs/system/devices/cxl.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a..4c38223 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -111,7 +111,7 @@ Interfaces provided include: CXL Root Ports (CXL RP) ~~~~~~~~~~~~~~~~~~~~~~~ -A CXL Root Port servers te same purpose as a PCIe Root Port. +A CXL Root Port serves the same purpose as a PCIe Root Port. There are a number of CXL specific Designated Vendor Specific Extended Capabilities (DVSEC) in PCIe Configuration Space and associated component register access via PCI bars. |