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authorThomas Huth <huth@tuxfamily.org>2017-02-12 15:41:35 +0100
committerThomas Huth <huth@tuxfamily.org>2017-02-18 22:23:31 +0100
commit88b86983f3ec5d68afa6048bd6387c1997de3b3f (patch)
tree34ec144f0fc847fd33ae8d4588370e861aa4d364
parent22f2dbe7eaf3e12e38c9c21081d72bf09e83ef90 (diff)
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hw/m68k: QOMify the ColdFire interrupt controller
Use type_init() and friends to adapt the ColdFire interrupt controller to the latest QEMU device conventions. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
-rw-r--r--hw/m68k/mcf_intc.c48
1 files changed, 44 insertions, 4 deletions
diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c
index cf58132..8198afa 100644
--- a/hw/m68k/mcf_intc.c
+++ b/hw/m68k/mcf_intc.c
@@ -9,10 +9,16 @@
#include "qemu-common.h"
#include "cpu.h"
#include "hw/hw.h"
+#include "hw/sysbus.h"
#include "hw/m68k/mcf.h"
#include "exec/address-spaces.h"
+#define TYPE_MCF_INTC "mcf-intc"
+#define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC)
+
typedef struct {
+ SysBusDevice parent_obj;
+
MemoryRegion iomem;
uint64_t ipr;
uint64_t imr;
@@ -138,8 +144,10 @@ static void mcf_intc_set_irq(void *opaque, int irq, int level)
mcf_intc_update(s);
}
-static void mcf_intc_reset(mcf_intc_state *s)
+static void mcf_intc_reset(DeviceState *dev)
{
+ mcf_intc_state *s = MCF_INTC(dev);
+
s->imr = ~0ull;
s->ipr = 0;
s->ifr = 0;
@@ -154,17 +162,49 @@ static const MemoryRegionOps mcf_intc_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static void mcf_intc_instance_init(Object *obj)
+{
+ mcf_intc_state *s = MCF_INTC(obj);
+
+ memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100);
+}
+
+static void mcf_intc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+ dc->reset = mcf_intc_reset;
+}
+
+static const TypeInfo mcf_intc_gate_info = {
+ .name = TYPE_MCF_INTC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(mcf_intc_state),
+ .instance_init = mcf_intc_instance_init,
+ .class_init = mcf_intc_class_init,
+};
+
+static void mcf_intc_register_types(void)
+{
+ type_register_static(&mcf_intc_gate_info);
+}
+
+type_init(mcf_intc_register_types)
+
qemu_irq *mcf_intc_init(MemoryRegion *sysmem,
hwaddr base,
M68kCPU *cpu)
{
+ DeviceState *dev;
mcf_intc_state *s;
- s = g_malloc0(sizeof(mcf_intc_state));
+ dev = qdev_create(NULL, TYPE_MCF_INTC);
+ qdev_init_nofail(dev);
+
+ s = MCF_INTC(dev);
s->cpu = cpu;
- mcf_intc_reset(s);
- memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100);
memory_region_add_subregion(sysmem, base, &s->iomem);
return qemu_allocate_irqs(mcf_intc_set_irq, s, 64);