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authorHelge Deller <deller@gmx.de>2022-01-11 20:44:42 +0100
committerHelge Deller <deller@gmx.de>2022-02-02 18:46:41 +0100
commit87e126ea149ee3f19d64f054886f573dc6b8ddee (patch)
tree03dbb2a0dbdd8dd644778d4acd6a5ba03f5bfa49
parent097defeb12eed05e637436db65c117c4b6274f9d (diff)
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hw/hppa: Allow up to 16 emulated CPUs
This brings the hppa_hardware.h file in sync with the copy in the SeaBIOS-hppa sources. In order to support up to 16 CPUs, it's required to move the HPA for MEMORY_HPA out of the address space of the new 16th CPU. The new address of 0xfffff000 worked well for Linux and HP-UX, while other addresses close to the former 0xfffbf000 area are used by the architecture for local and global broadcasts. The PIM_STORAGE_SIZE constant is used in SeaBIOS sources and is relevant for the TOC/NMI feature. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--hw/hppa/hppa_hardware.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h
index bc25889..5edf577 100644
--- a/hw/hppa/hppa_hardware.h
+++ b/hw/hppa/hppa_hardware.h
@@ -25,7 +25,7 @@
#define LASI_GFX_HPA 0xf8000000
#define ARTIST_FB_ADDR 0xf9000000
#define CPU_HPA 0xfffb0000
-#define MEMORY_HPA 0xfffbf000
+#define MEMORY_HPA 0xfffff000
#define PCI_HPA DINO_HPA /* PCI bus */
#define IDE_HPA 0xf9000000 /* Boot disc controller */
@@ -43,9 +43,10 @@
#define PORT_SERIAL1 (DINO_UART_HPA + 0x800)
#define PORT_SERIAL2 (LASI_UART_HPA + 0x800)
-#define HPPA_MAX_CPUS 8 /* max. number of SMP CPUs */
+#define HPPA_MAX_CPUS 16 /* max. number of SMP CPUs */
#define CPU_CLOCK_MHZ 250 /* emulate a 250 MHz CPU */
#define CPU_HPA_CR_REG 7 /* store CPU HPA in cr7 (SeaBIOS internal) */
+#define PIM_STORAGE_SIZE 600 /* storage size of pdc_pim_toc_struct (64bit) */
#endif