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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-08-31 09:45:15 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-08-31 09:45:15 +0100 |
| commit | 87da10b45ce50b55c0306862a511c77243b1b065 (patch) | |
| tree | ba10730f9aa6927b94fcf88a39020975c3c62525 | |
| parent | 6d482423fcecb34056013268fa552b1ce2efcfeb (diff) | |
| download | qemu-87da10b45ce50b55c0306862a511c77243b1b065.zip qemu-87da10b45ce50b55c0306862a511c77243b1b065.tar.gz qemu-87da10b45ce50b55c0306862a511c77243b1b065.tar.bz2 | |
target/arm: Apply access checks to neoverse-v1 special registers
There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230811214031.171020-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/cpu64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index bc3db79..b0cac05 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -560,7 +560,8 @@ static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, - .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, + .accessfn = access_actlr_w }, { .name = "CPUPPMCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 0, .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |