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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-01-21 13:04:01 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-09 17:00:47 +0100 |
| commit | 85edafe385f538ce3a84ed478faea12e28ab1720 (patch) | |
| tree | d7f691cac80e546aa99e613e78e35d5aba372326 | |
| parent | 55f29126b6f980f759e0bdab2e83361b98232305 (diff) | |
| download | qemu-85edafe385f538ce3a84ed478faea12e28ab1720.zip qemu-85edafe385f538ce3a84ed478faea12e28ab1720.tar.gz qemu-85edafe385f538ce3a84ed478faea12e28ab1720.tar.bz2 | |
target/mips: Move has_work() from CPUClass to SysemuCPUOps
Move has_work() from CPUClass to SysemuCPUOps and
cpu_mips_hw_interrupts_enabled() to system.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250125170125.32855-14-philmd@linaro.org>
| -rw-r--r-- | target/mips/cpu.c | 4 | ||||
| -rw-r--r-- | target/mips/internal.h | 4 |
2 files changed, 5 insertions, 3 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e762986..b207106 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -132,6 +132,7 @@ static vaddr mips_cpu_get_pc(CPUState *cs) return cpu->env.active_tc.PC; } +#if !defined(CONFIG_USER_ONLY) static bool mips_cpu_has_work(CPUState *cs) { CPUMIPSState *env = cpu_env(cs); @@ -177,6 +178,7 @@ static bool mips_cpu_has_work(CPUState *cs) } return has_work; } +#endif /* !CONFIG_USER_ONLY */ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) { @@ -534,6 +536,7 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps mips_sysemu_ops = { + .has_work = mips_cpu_has_work, .get_phys_page_debug = mips_cpu_get_phys_page_debug, .legacy_vmsd = &vmstate_mips_cpu, }; @@ -577,7 +580,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) &mcc->parent_phases); cc->class_by_name = mips_cpu_class_by_name; - cc->has_work = mips_cpu_has_work; cc->mmu_index = mips_cpu_mmu_index; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; diff --git a/target/mips/internal.h b/target/mips/internal.h index 91c786c..28eb289 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -162,8 +162,6 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); extern const VMStateDescription vmstate_mips_cpu; -#endif /* !CONFIG_USER_ONLY */ - static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { return (env->CP0_Status & (1 << CP0St_IE)) && @@ -206,6 +204,8 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) return r; } +#endif /* !CONFIG_USER_ONLY */ + void msa_reset(CPUMIPSState *env); /* cp0_timer.c */ |