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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-04-08 17:24:02 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-04-30 11:16:49 +0100 |
| commit | 8196fe9d83d6519128b514f332418bae06513970 (patch) | |
| tree | ef7ba90be1eaed8a1a8aab69e6edde42bd0bb8be | |
| parent | bf559ee4025adaf9713e22def862d31f1db5994e (diff) | |
| download | qemu-8196fe9d83d6519128b514f332418bae06513970.zip qemu-8196fe9d83d6519128b514f332418bae06513970.tar.gz qemu-8196fe9d83d6519128b514f332418bae06513970.tar.bz2 | |
target/arm: Make Thumb store insns UNDEF for Rn==1111
The Arm ARM specifies that for Thumb encodings of the various plain
store insns, if the Rn field is 1111 then we must UNDEF. This is
different from the Arm encodings, where this case is either
UNPREDICTABLE or has well-defined behaviour. The exclusive stores,
store-release and STRD do not have this UNDEF case for any encoding.
Enforce the UNDEF for this case in the Thumb plain store insns.
Fixes: https://bugs.launchpad.net/qemu/+bug/1922887
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210408162402.5822-1-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/translate.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 7103da2..68809e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6476,6 +6476,14 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; TCGv_i32 addr, tmp; + /* + * In Thumb encodings of stores Rn=1111 is UNDEF; for Arm it + * is either UNPREDICTABLE or has defined behaviour + */ + if (s->thumb && a->rn == 15) { + return false; + } + addr = op_addr_rr_pre(s, a); tmp = load_reg(s, a->rt); @@ -6620,6 +6628,14 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; TCGv_i32 addr, tmp; + /* + * In Thumb encodings of stores Rn=1111 is UNDEF; for Arm it + * is either UNPREDICTABLE or has defined behaviour + */ + if (s->thumb && a->rn == 15) { + return false; + } + addr = op_addr_ri_pre(s, a); tmp = load_reg(s, a->rt); |