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authorRichard Henderson <richard.henderson@linaro.org>2021-01-29 21:30:04 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-03-17 07:24:44 -0600
commit817cadd6ee952908aa46196ddb64522b2d6f58f2 (patch)
tree312384df3dba9255bfebdef1adb9eeedc2624c08
parentf28ca03ed5c452a5f81b1f4c84360a8bbdee617f (diff)
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tcg/tci: Split out tci_args_rrrrrc
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--tcg/tci.c25
1 files changed, 19 insertions, 6 deletions
diff --git a/tcg/tci.c b/tcg/tci.c
index e323351..22ede40 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -223,6 +223,19 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
*c3 = tci_read_b(tb_ptr);
}
+#if TCG_TARGET_REG_BITS == 32
+static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
+ TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+ *r4 = tci_read_r(tb_ptr);
+ *c5 = tci_read_b(tb_ptr);
+}
+#endif
+
static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
{
bool result = false;
@@ -385,7 +398,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
uint32_t tmp32;
uint64_t tmp64;
#if TCG_TARGET_REG_BITS == 32
- uint64_t v64;
+ TCGReg r3, r4;
+ uint64_t v64, T1, T2;
#endif
TCGMemOpIdx oi;
int32_t ofs;
@@ -434,11 +448,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_setcond2_i32:
- t0 = *tb_ptr++;
- tmp64 = tci_read_r64(regs, &tb_ptr);
- v64 = tci_read_r64(regs, &tb_ptr);
- condition = *tb_ptr++;
- tci_write_reg(regs, t0, tci_compare64(tmp64, v64, condition));
+ tci_args_rrrrrc(&tb_ptr, &r0, &r1, &r2, &r3, &r4, &condition);
+ T1 = tci_uint64(regs[r2], regs[r1]);
+ T2 = tci_uint64(regs[r4], regs[r3]);
+ regs[r0] = tci_compare64(T1, T2, condition);
break;
#elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64: