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| author | Tom Musta <tommusta@gmail.com> | 2014-03-31 16:03:57 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-04-08 11:20:01 +0200 |
| commit | 80189035de73f30e42a7f933c45cccfc4b0c56e9 (patch) | |
| tree | f6aa76e916362c32fe0c60c3aad24041995f4f17 | |
| parent | 0453099b7d20c9fc2946ed74f1d965ae4d173d19 (diff) | |
| download | qemu-80189035de73f30e42a7f933c45cccfc4b0c56e9.zip qemu-80189035de73f30e42a7f933c45cccfc4b0c56e9.tar.gz qemu-80189035de73f30e42a7f933c45cccfc4b0c56e9.tar.bz2 | |
target-ppc: Define Endian-Correct Accessors for VSR Field Access
This change defines accessors for VSR doubleword and word fields that
are correct from a host Endian perspective. This allows code to
use the Power ISA indexing numbers in code.
For example, the xscvdpsxws instruction has a target VSR that looks
like this:
0 32 64 127
+-----------+--------+-----------+-----------+
| undefined | SW | undefined | undefined |
+-----------+--------+-----------+-----------+
VSX helper code will use VsrW(1) to access this field.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/fpu_helper.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 691d572..d79aae9 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1782,6 +1782,14 @@ typedef union _ppc_vsr_t { float64 f64[2]; } ppc_vsr_t; +#if defined(HOST_WORDS_BIGENDIAN) +#define VsrW(i) u32[i] +#define VsrD(i) u64[i] +#else +#define VsrW(i) u32[3-(i)] +#define VsrD(i) u64[1-(i)] +#endif + static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { |