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| author | Paolo Bonzini <pbonzini@redhat.com> | 2025-02-06 13:41:49 +0100 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2025-05-20 08:18:53 +0200 |
| commit | 7f9e15d82d21714a2c82aff8869b8ef9aa191c98 (patch) | |
| tree | 490a8b3279a6fa2b7787ae0eb3e842621b4b97e4 | |
| parent | 5fd23f20e12a56e7ac2dabbe9570fb2f10d7c5b4 (diff) | |
| download | qemu-7f9e15d82d21714a2c82aff8869b8ef9aa191c98.zip qemu-7f9e15d82d21714a2c82aff8869b8ef9aa191c98.tar.gz qemu-7f9e15d82d21714a2c82aff8869b8ef9aa191c98.tar.bz2 | |
target/riscv: merge riscv_cpu_class_init with the class_base function
Since all TYPE_RISCV_CPU subclasses support a class_data of type
RISCVCPUDef, process it even before calling the .class_init function
for the subclasses.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | target/riscv/cpu.c | 21 |
1 files changed, 10 insertions, 11 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 22e3a22..334791e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3080,15 +3080,18 @@ static void riscv_cpu_class_base_init(ObjectClass *c, const void *data) } else { mcc->def = g_new0(RISCVCPUDef, 1); } -} -static void riscv_cpu_class_init(ObjectClass *c, const void *data) -{ - RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); - const RISCVCPUDef *def = data; + if (data) { + const RISCVCPUDef *def = data; + if (def->misa_mxl_max) { + assert(def->misa_mxl_max <= MXL_RV128); + mcc->def->misa_mxl_max = def->misa_mxl_max; + } + } - mcc->def->misa_mxl_max = def->misa_mxl_max; - riscv_cpu_validate_misa_mxl(mcc); + if (!object_class_is_abstract(c)) { + riscv_cpu_validate_misa_mxl(mcc); + } } static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, @@ -3188,7 +3191,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_DYNAMIC_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &(const RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }, \ @@ -3199,7 +3201,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_VENDOR_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &(const RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }, \ @@ -3210,7 +3211,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &(const RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }, \ @@ -3221,7 +3221,6 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) .name = (type_name), \ .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ - .class_init = riscv_cpu_class_init, \ .class_data = &(const RISCVCPUDef) { \ .misa_mxl_max = (misa_mxl_max_), \ }, \ |