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| author | Richard Henderson <rth@twiddle.net> | 2013-11-06 11:34:38 +1000 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-01-07 11:40:13 -0800 |
| commit | 7effd62514fa42c3c6c9be15a97c98a5f76748b7 (patch) | |
| tree | e02ace4a24a821a95cbccd7d0ce8404413273d95 | |
| parent | ab4e4aec78657138312948359055e20f6266bd17 (diff) | |
| download | qemu-7effd62514fa42c3c6c9be15a97c98a5f76748b7.zip qemu-7effd62514fa42c3c6c9be15a97c98a5f76748b7.tar.gz qemu-7effd62514fa42c3c6c9be15a97c98a5f76748b7.tar.bz2 | |
target-i386: Tidy addr16 code in gen_lea_modrm
Unlike the addr32, there was no bug. But we can use the same
technique to reduce the number of TCG ops.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target-i386/translate.c | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/target-i386/translate.c b/target-i386/translate.c index 9f38adf..8673f95 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2028,51 +2028,49 @@ static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm) break; default: case 2: - disp = cpu_lduw_code(env, s->pc); + disp = (int16_t)cpu_lduw_code(env, s->pc); s->pc += 2; break; } - switch(rm) { + + sum = cpu_A0; + switch (rm) { case 0: - gen_op_movl_A0_reg(R_EBX); - gen_op_addl_A0_reg_sN(0, R_ESI); + tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_ESI]); break; case 1: - gen_op_movl_A0_reg(R_EBX); - gen_op_addl_A0_reg_sN(0, R_EDI); + tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBX], cpu_regs[R_EDI]); break; case 2: - gen_op_movl_A0_reg(R_EBP); - gen_op_addl_A0_reg_sN(0, R_ESI); + tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_ESI]); break; case 3: - gen_op_movl_A0_reg(R_EBP); - gen_op_addl_A0_reg_sN(0, R_EDI); + tcg_gen_add_tl(cpu_A0, cpu_regs[R_EBP], cpu_regs[R_EDI]); break; case 4: - gen_op_movl_A0_reg(R_ESI); + sum = cpu_regs[R_ESI]; break; case 5: - gen_op_movl_A0_reg(R_EDI); + sum = cpu_regs[R_EDI]; break; case 6: - gen_op_movl_A0_reg(R_EBP); + sum = cpu_regs[R_EBP]; break; default: case 7: - gen_op_movl_A0_reg(R_EBX); + sum = cpu_regs[R_EBX]; break; } - if (disp != 0) - gen_op_addl_A0_im(disp); + tcg_gen_addi_tl(cpu_A0, sum, disp); tcg_gen_ext16u_tl(cpu_A0, cpu_A0); no_rm: if (must_add_seg) { if (override < 0) { - if (rm == 2 || rm == 3 || rm == 6) + if (rm == 2 || rm == 3 || rm == 6) { override = R_SS; - else + } else { override = R_DS; + } } gen_op_addl_A0_seg(s, override); } |