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authorPhilippe Mathieu-Daudé <philmd@linaro.org>2024-01-10 09:32:33 +0100
committerPhilippe Mathieu-Daudé <philmd@linaro.org>2024-01-19 12:28:59 +0100
commit7ebbd9d0b6a6b692371a3f31b9cc937824bed92b (patch)
tree05427cad573c07ca06f500801e63a111b225da2c
parente129593f6fc98d4fa14d0241061b5f556c9a4347 (diff)
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target/riscv: Rename tcg_cpu_FOO() to include 'riscv'
The tcg_cpu_FOO() names are riscv specific, so rename them as riscv_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240111120221.35072-6-philmd@linaro.org>
-rw-r--r--target/riscv/tcg/tcg-cpu.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 14133ff..994ca1c 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -929,7 +929,7 @@ static bool riscv_cpu_is_vendor(Object *cpu_obj)
* -> cpu_exec_realizefn()
* -> tcg_cpu_realize() (via accel_cpu_common_realize())
*/
-static bool tcg_cpu_realize(CPUState *cs, Error **errp)
+static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
{
RISCVCPU *cpu = RISCV_CPU(cs);
Error *local_err = NULL;
@@ -1372,7 +1372,7 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
}
-static void tcg_cpu_instance_init(CPUState *cs)
+static void riscv_tcg_cpu_instance_init(CPUState *cs)
{
RISCVCPU *cpu = RISCV_CPU(cs);
Object *obj = OBJECT(cpu);
@@ -1386,7 +1386,7 @@ static void tcg_cpu_instance_init(CPUState *cs)
}
}
-static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
+static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/*
* All cpus use the same set of operations.
@@ -1394,30 +1394,30 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
cc->tcg_ops = &riscv_tcg_ops;
}
-static void tcg_cpu_class_init(CPUClass *cc)
+static void riscv_tcg_cpu_class_init(CPUClass *cc)
{
- cc->init_accel_cpu = tcg_cpu_init_ops;
+ cc->init_accel_cpu = riscv_tcg_cpu_init_ops;
}
-static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
+static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data)
{
AccelCPUClass *acc = ACCEL_CPU_CLASS(oc);
- acc->cpu_class_init = tcg_cpu_class_init;
- acc->cpu_instance_init = tcg_cpu_instance_init;
- acc->cpu_target_realize = tcg_cpu_realize;
+ acc->cpu_class_init = riscv_tcg_cpu_class_init;
+ acc->cpu_instance_init = riscv_tcg_cpu_instance_init;
+ acc->cpu_target_realize = riscv_tcg_cpu_realize;
}
-static const TypeInfo tcg_cpu_accel_type_info = {
+static const TypeInfo riscv_tcg_cpu_accel_type_info = {
.name = ACCEL_CPU_NAME("tcg"),
.parent = TYPE_ACCEL_CPU,
- .class_init = tcg_cpu_accel_class_init,
+ .class_init = riscv_tcg_cpu_accel_class_init,
.abstract = true,
};
-static void tcg_cpu_accel_register_types(void)
+static void riscv_tcg_cpu_accel_register_types(void)
{
- type_register_static(&tcg_cpu_accel_type_info);
+ type_register_static(&riscv_tcg_cpu_accel_type_info);
}
-type_init(tcg_cpu_accel_register_types);
+type_init(riscv_tcg_cpu_accel_register_types);