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author | Inès Varhol <ines.varhol@telecom-paris.fr> | 2024-01-09 20:41:58 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2024-01-15 17:12:22 +0000 |
commit | 7dfe2312e4653dd796dc2731668ad65237563e39 (patch) | |
tree | a51666de567eb8caaff4a01aee326259ba52f23c | |
parent | 20936684b6dd02eec35591661553a57f3515cf5b (diff) | |
download | qemu-7dfe2312e4653dd796dc2731668ad65237563e39.zip qemu-7dfe2312e4653dd796dc2731668ad65237563e39.tar.gz qemu-7dfe2312e4653dd796dc2731668ad65237563e39.tar.bz2 |
hw/arm: Connect STM32L4x5 SYSCFG to STM32L4x5 SoC
The SYSCFG input GPIOs aren't connected yet. When the STM32L4x5 GPIO
device will be implemented, its output GPIOs will be connected to the
SYSCFG input GPIOs.
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr>
Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20240109194438.70934-3-ines.varhol@telecom-paris.fr
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | hw/arm/Kconfig | 1 | ||||
-rw-r--r-- | hw/arm/stm32l4x5_soc.c | 21 | ||||
-rw-r--r-- | include/hw/arm/stm32l4x5_soc.h | 2 |
3 files changed, 23 insertions, 1 deletions
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index da9c6e5..218b454 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -459,6 +459,7 @@ config STM32L4X5_SOC bool select ARM_V7M select OR_IRQ + select STM32L4X5_SYSCFG select STM32L4X5_EXTI config XLNX_ZYNQMP_ARM diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 756eb69..f470ff7 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -37,6 +37,7 @@ #define SRAM2_SIZE (32 * KiB) #define EXTI_ADDR 0x40010400 +#define SYSCFG_ADDR 0x40010000 #define NUM_EXTI_IRQ 40 /* Match exti line connections with their CPU IRQ number */ @@ -80,6 +81,7 @@ static void stm32l4x5_soc_initfn(Object *obj) Stm32l4x5SocState *s = STM32L4X5_SOC(obj); object_initialize_child(obj, "exti", &s->exti, TYPE_STM32L4X5_EXTI); + object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32L4X5_SYSCFG); s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0); @@ -155,6 +157,19 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) return; } + /* System configuration controller */ + busdev = SYS_BUS_DEVICE(&s->syscfg); + if (!sysbus_realize(busdev, errp)) { + return; + } + sysbus_mmio_map(busdev, 0, SYSCFG_ADDR); + /* + * TODO: when the GPIO device is implemented, connect it + * to SYCFG using `qdev_connect_gpio_out`, NUM_GPIOS and + * GPIO_NUM_PINS. + */ + + /* EXTI device */ busdev = SYS_BUS_DEVICE(&s->exti); if (!sysbus_realize(busdev, errp)) { return; @@ -164,6 +179,11 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i])); } + for (unsigned i = 0; i < 16; i++) { + qdev_connect_gpio_out(DEVICE(&s->syscfg), i, + qdev_get_gpio_in(DEVICE(&s->exti), i)); + } + /* APB1 BUS */ create_unimplemented_device("TIM2", 0x40000000, 0x400); create_unimplemented_device("TIM3", 0x40000400, 0x400); @@ -201,7 +221,6 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc, Error **errp) /* RESERVED: 0x40009800, 0x6800 */ /* APB2 BUS */ - create_unimplemented_device("SYSCFG", 0x40010000, 0x30); create_unimplemented_device("VREFBUF", 0x40010030, 0x1D0); create_unimplemented_device("COMP", 0x40010200, 0x200); /* RESERVED: 0x40010800, 0x1400 */ diff --git a/include/hw/arm/stm32l4x5_soc.h b/include/hw/arm/stm32l4x5_soc.h index f730556..baf7041 100644 --- a/include/hw/arm/stm32l4x5_soc.h +++ b/include/hw/arm/stm32l4x5_soc.h @@ -26,6 +26,7 @@ #include "exec/memory.h" #include "hw/arm/armv7m.h" +#include "hw/misc/stm32l4x5_syscfg.h" #include "hw/misc/stm32l4x5_exti.h" #include "qom/object.h" @@ -41,6 +42,7 @@ struct Stm32l4x5SocState { ARMv7MState armv7m; Stm32l4x5ExtiState exti; + Stm32l4x5SyscfgState syscfg; MemoryRegion sram1; MemoryRegion sram2; |