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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-03 02:19:31 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-18 00:41:36 +0200 |
| commit | 7da51cb391bc1100b941d04a0e9fec2cdc5b9632 (patch) | |
| tree | c967c509863a2f37afcd721e4b4f4fea21cf76d2 | |
| parent | 723038999ef42fec4f845841d2d35a52f9ab1dbe (diff) | |
| download | qemu-7da51cb391bc1100b941d04a0e9fec2cdc5b9632.zip qemu-7da51cb391bc1100b941d04a0e9fec2cdc5b9632.tar.gz qemu-7da51cb391bc1100b941d04a0e9fec2cdc5b9632.tar.bz2 | |
target/mips: Remove unused register from MSA 2R/2RF instruction format
Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added
the MSA 2R/2RF instructions. However these instructions don't use any
target vector register, so remove the unused TCG temporaries.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211003175743.3738710-2-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/msa_translate.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 8170a8d..ee64241 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -1942,13 +1942,11 @@ static void gen_msa_2r(DisasContext *ctx) { #define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0x7 << 18))) - uint8_t wt = (ctx->opcode >> 16) & 0x1f; uint8_t ws = (ctx->opcode >> 11) & 0x1f; uint8_t wd = (ctx->opcode >> 6) & 0x1f; uint8_t df = (ctx->opcode >> 16) & 0x3; TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); TCGv_i32 tdf = tcg_const_i32(df); switch (MASK_MSA_2R(ctx->opcode)) { @@ -2018,7 +2016,6 @@ static void gen_msa_2r(DisasContext *ctx) tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); tcg_temp_free_i32(tdf); } @@ -2026,13 +2023,11 @@ static void gen_msa_2rf(DisasContext *ctx) { #define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \ (op & (0xf << 17))) - uint8_t wt = (ctx->opcode >> 16) & 0x1f; uint8_t ws = (ctx->opcode >> 11) & 0x1f; uint8_t wd = (ctx->opcode >> 6) & 0x1f; uint8_t df = (ctx->opcode >> 16) & 0x1; TCGv_i32 twd = tcg_const_i32(wd); TCGv_i32 tws = tcg_const_i32(ws); - TCGv_i32 twt = tcg_const_i32(wt); /* adjust df value for floating-point instruction */ TCGv_i32 tdf = tcg_const_i32(df + 2); @@ -2089,7 +2084,6 @@ static void gen_msa_2rf(DisasContext *ctx) tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); - tcg_temp_free_i32(twt); tcg_temp_free_i32(tdf); } |