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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2023-02-24 12:08:50 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-03-01 17:28:16 -0800 |
| commit | 7a6613da99ccb0a80adda550722df387736d77da (patch) | |
| tree | 370efc410de1592e2a0d434d96272728710ba597 | |
| parent | 0d190bd3948402257b8ca218cd63ee8bbb78b76c (diff) | |
| download | qemu-7a6613da99ccb0a80adda550722df387736d77da.zip qemu-7a6613da99ccb0a80adda550722df387736d77da.tar.gz qemu-7a6613da99ccb0a80adda550722df387736d77da.tar.bz2 | |
target/riscv: Add *envcfg.PBMTE related check in address translation
menvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in S-mode and G-stage address translation.
henvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in VS-stage address translation.
Set *envcfg.PBMTE default true for backward compatibility.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224040852.37109-5-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | target/riscv/cpu.c | 3 | ||||
| -rw-r--r-- | target/riscv/cpu_helper.c | 10 |
2 files changed, 11 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93b52b8..c8580f0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -613,6 +613,9 @@ static void riscv_cpu_reset_hold(Object *obj) env->bins = 0; env->two_stage_lookup = false; + env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0); + env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0); + /* Initialized default priorities of local interrupts. */ for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { iprio = riscv_cpu_default_priority(i); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3a9472a..44a8f26 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -936,9 +936,15 @@ restart: return TRANSLATE_FAIL; } + bool pbmte = env->menvcfg & MENVCFG_PBMTE; + + if (first_stage && two_stage && riscv_cpu_virt_enabled(env)) { + pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE); + } + if (riscv_cpu_sxl(env) == MXL_RV32) { ppn = pte >> PTE_PPN_SHIFT; - } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { + } else if (pbmte || cpu->cfg.ext_svnapot) { ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn = pte >> PTE_PPN_SHIFT; @@ -950,7 +956,7 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; - } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { + } else if (!pbmte && (pte & PTE_PBMT)) { return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ |