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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2025-04-29 09:44:20 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2025-05-19 13:42:47 +1000 |
| commit | 775ac57e0a54b9127bd2ad005675772870cd1932 (patch) | |
| tree | 4bd0899dbf1106d019a33f4f711b7ec818378b36 | |
| parent | 86b8c3821496898cd3bd8eaa1bac71f5c784a2db (diff) | |
| download | qemu-775ac57e0a54b9127bd2ad005675772870cd1932.zip qemu-775ac57e0a54b9127bd2ad005675772870cd1932.tar.gz qemu-775ac57e0a54b9127bd2ad005675772870cd1932.tar.bz2 | |
target/riscv/kvm: read/write KVM regs via env size
We're going to add support for scounteren in the next patch. KVM defines
as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit
field. This will cause the current code to read/write a 64 bit CSR in a
32 bit field when running in a 64 bit CPU.
To prevent that, change the current logic to honor the size of the QEMU
storage instead of the KVM CSR reg.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20250429124421.223883-9-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/kvm/kvm-cpu.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 0e34382..ca171d5 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -135,6 +135,7 @@ typedef struct KVMCPUConfig { const char *description; target_ulong offset; uint64_t kvm_reg_id; + uint32_t prop_size; bool user_set; bool supported; } KVMCPUConfig; @@ -237,6 +238,7 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs) #define KVM_CSR_CFG(_name, _env_prop, reg_id) \ {.name = _name, .offset = ENV_CSR_OFFSET(_env_prop), \ + .prop_size = sizeof(((CPURISCVState *)0)->_env_prop), \ .kvm_reg_id = reg_id} static KVMCPUConfig kvm_csr_cfgs[] = { @@ -646,9 +648,9 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) return ret; } - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { - kvm_cpu_csr_set_u32(cpu, csr_cfg, reg); - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint64_t)) { + if (csr_cfg->prop_size == sizeof(uint32_t)) { + kvm_cpu_csr_set_u32(cpu, csr_cfg, (uint32_t)reg); + } else if (csr_cfg->prop_size == sizeof(uint64_t)) { kvm_cpu_csr_set_u64(cpu, csr_cfg, reg); } else { g_assert_not_reached(); @@ -671,9 +673,9 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) continue; } - if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint32_t)) { + if (csr_cfg->prop_size == sizeof(uint32_t)) { reg = kvm_cpu_csr_get_u32(cpu, csr_cfg); - } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) == sizeof(uint64_t)) { + } else if (csr_cfg->prop_size == sizeof(uint64_t)) { reg = kvm_cpu_csr_get_u64(cpu, csr_cfg); } else { g_assert_not_reached(); |