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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-08-22 14:23:49 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-09-14 11:19:40 +0100 |
| commit | 76e25d41d44c49eb0fe399064a719702a3023102 (patch) | |
| tree | 8057b5d34ad0ab90188943fd45b4cc78e65b0463 | |
| parent | bb7d902154f7f17c9127631c42a21fbbc805cb40 (diff) | |
| download | qemu-76e25d41d44c49eb0fe399064a719702a3023102.zip qemu-76e25d41d44c49eb0fe399064a719702a3023102.tar.gz qemu-76e25d41d44c49eb0fe399064a719702a3023102.tar.bz2 | |
target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows
When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/arm/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 7ff03f1..e4824e0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1186,7 +1186,7 @@ static void pmccntr_op_start(CPUARMState *env) uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ 1ull << 63 : 1ull << 31; if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { - env->cp15.c9_pmovsr |= (1 << 31); + env->cp15.c9_pmovsr |= (1ULL << 31); pmu_update_irq(env); } |