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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-12-13 16:43:40 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-12-15 12:56:03 -0600 |
| commit | 766bade2da0f9b1338cbe72aea114cd0922acfc5 (patch) | |
| tree | ee29a71fb6f2784202c8b767c1f173249954b215 | |
| parent | 4ef4c30d2ef6d1dcfc58512e6ed273244dcd72cd (diff) | |
| download | qemu-766bade2da0f9b1338cbe72aea114cd0922acfc5.zip qemu-766bade2da0f9b1338cbe72aea114cd0922acfc5.tar.gz qemu-766bade2da0f9b1338cbe72aea114cd0922acfc5.tar.bz2 | |
hw/riscv: Constify all Property
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | hw/riscv/opentitan.c | 2 | ||||
| -rw-r--r-- | hw/riscv/riscv-iommu-pci.c | 2 | ||||
| -rw-r--r-- | hw/riscv/riscv-iommu.c | 2 | ||||
| -rw-r--r-- | hw/riscv/riscv_hart.c | 2 | ||||
| -rw-r--r-- | hw/riscv/sifive_u.c | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e2830e9..8ce85ea 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -306,7 +306,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); } -static Property lowrisc_ibex_soc_props[] = { +static const Property lowrisc_ibex_soc_props[] = { DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400), DEFINE_PROP_END_OF_LIST() }; diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index a422425..a695314 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -157,7 +157,7 @@ static void riscv_iommu_pci_init(Object *obj) iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS; } -static Property riscv_iommu_pci_properties[] = { +static const Property riscv_iommu_pci_properties[] = { DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id, PCI_VENDOR_ID_REDHAT), DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index bbc9542..07fed36 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2235,7 +2235,7 @@ static void riscv_iommu_unrealize(DeviceState *dev) g_hash_table_unref(s->ctx_cache); } -static Property riscv_iommu_properties[] = { +static const Property riscv_iommu_properties[] = { DEFINE_PROP_UINT32("version", RISCVIOMMUState, version, RISCV_IOMMU_SPEC_DOT_VER), DEFINE_PROP_UINT32("bus", RISCVIOMMUState, bus, 0x0), diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2a..0df4547 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -27,7 +27,7 @@ #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" -static Property riscv_harts_props[] = { +static const Property riscv_harts_props[] = { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c5e7412..124ffd4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -936,7 +936,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ)); } -static Property sifive_u_soc_props[] = { +static const Property sifive_u_soc_props[] = { DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), DEFINE_PROP_END_OF_LIST() |