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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-12-11 10:29:50 -0600 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-12-13 13:39:23 +0000 |
| commit | 7261f2a7a75ab9be4aa3f8a7896f21a39df74006 (patch) | |
| tree | ea7f446977249bfd46f67e936bcf12f82b3aec80 | |
| parent | cc0db9dea0e02373a7440ec6d19a00b0f70bbc9e (diff) | |
| download | qemu-7261f2a7a75ab9be4aa3f8a7896f21a39df74006.zip qemu-7261f2a7a75ab9be4aa3f8a7896f21a39df74006.tar.gz qemu-7261f2a7a75ab9be4aa3f8a7896f21a39df74006.tar.bz2 | |
target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt
These opcodes are only supported as vector operations,
not as advsimd scalar. Set only_in_vector, and remove
the unreachable implementation of scalar fneg.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20241211163036.2297116-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a99f3d0..3c17845 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10816,10 +10816,13 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) break; case 0x2f: /* FABS */ case 0x6f: /* FNEG */ + only_in_vector = true; need_fpst = false; break; case 0x7d: /* FRSQRTE */ + break; case 0x7f: /* FSQRT (vector) */ + only_in_vector = true; break; default: unallocated_encoding(s); @@ -10877,9 +10880,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; - case 0x6f: /* FNEG */ - tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); - break; case 0x7d: /* FRSQRTE */ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); break; |