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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-08-05 04:09:15 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2022-02-09 08:59:06 +1100 |
| commit | 684db2a0b04ff024d0a275de85982fe5892185d3 (patch) | |
| tree | 5524d1f1421316f918944b60c35278bebe8c698b | |
| parent | 92840d06faeed2038b90d5b168c18d73ca3a44b8 (diff) | |
| download | qemu-684db2a0b04ff024d0a275de85982fe5892185d3.zip qemu-684db2a0b04ff024d0a275de85982fe5892185d3.tar.gz qemu-684db2a0b04ff024d0a275de85982fe5892185d3.tar.bz2 | |
tcg/sparc: Improve code gen for shifted 32-bit constants
We had code for checking for 13 and 21-bit shifted constants,
but we can do better and allow 32-bit shifted constants.
This is still 2 insns shorter than the full 64-bit sequence.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/sparc/tcg-target.c.inc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc index 7a8f20e..ed2f4ec 100644 --- a/tcg/sparc/tcg-target.c.inc +++ b/tcg/sparc/tcg-target.c.inc @@ -462,17 +462,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } - /* A 21-bit constant, shifted. */ + /* A 32-bit constant, shifted. */ lsb = ctz64(arg); test = (tcg_target_long)arg >> lsb; - if (check_fit_tl(test, 13)) { - tcg_out_movi_imm13(s, ret, test); - tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); - return; - } else if (lsb > 10 && test == extract64(test, 0, 21)) { + if (lsb > 10 && test == extract64(test, 0, 21)) { tcg_out_sethi(s, ret, test << 10); tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX); return; + } else if (test == (uint32_t)test || test == (int32_t)test) { + tcg_out_movi_int(s, TCG_TYPE_I64, ret, test, in_prologue, scratch); + tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX); + return; } /* A 64-bit constant decomposed into 2 32-bit pieces. */ |