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| author | Richard Henderson <rth@twiddle.net> | 2013-02-10 10:30:46 -0800 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2013-03-05 11:58:48 +0100 |
| commit | 68473f15d4c9948986618f63828825beafcaf1cf (patch) | |
| tree | 258dfe2e98960f3b42d80974238b6e0db675d578 | |
| parent | ff4f7382815d31933fe0cbedce03270e4b62b771 (diff) | |
| download | qemu-68473f15d4c9948986618f63828825beafcaf1cf.zip qemu-68473f15d4c9948986618f63828825beafcaf1cf.tar.gz qemu-68473f15d4c9948986618f63828825beafcaf1cf.tar.bz2 | |
mips64-linux-user: Enable 64-bit address mode and fpu
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/translate.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index a51f430..694f07c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15944,6 +15944,14 @@ void cpu_state_reset(CPUMIPSState *env) #if defined(CONFIG_USER_ONLY) env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); +# ifdef TARGET_MIPS64 + /* Enable 64-bit register mode. */ + env->CP0_Status |= (1 << CP0St_PX); +# endif +# ifdef TARGET_ABI_MIPSN64 + /* Enable 64-bit address mode. */ + env->CP0_Status |= (1 << CP0St_UX); +# endif /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR hardware registers. */ env->CP0_HWREna |= 0x0000000F; @@ -15953,6 +15961,10 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { env->CP0_Status |= (1 << CP0St_MX); } + /* Enable 64-bit FPU if the target cpu supports it. */ + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->CP0_Status |= (1 << CP0St_FR); + } #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, |