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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2022-03-05 07:16:46 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-03-05 07:16:46 +0100 |
| commit | 68455cf59394267363b090a1828b6c52994a4ee3 (patch) | |
| tree | b964603cfd64103c8d43e0744ef6e745a3e9bb1d | |
| parent | 63c2b746bebef3ec9de4f29d5beeea4ee809c892 (diff) | |
| download | qemu-68455cf59394267363b090a1828b6c52994a4ee3.zip qemu-68455cf59394267363b090a1828b6c52994a4ee3.tar.gz qemu-68455cf59394267363b090a1828b6c52994a4ee3.tar.bz2 | |
tests/tcg/ppc64le: Use Altivec register names in clobber list
LLVM/Clang doesn't know the VSX registers when compiling with
-mabi=elfv1. Use only registers >= 32 and list them with their Altivec
name.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220304165417.1981159-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | tests/tcg/ppc64le/non_signalling_xscv.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/non_signalling_xscv.c index 91e25ca..836df71 100644 --- a/tests/tcg/ppc64le/non_signalling_xscv.c +++ b/tests/tcg/ppc64le/non_signalling_xscv.c @@ -6,16 +6,16 @@ #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \ do { \ uint64_t th, tl, bh = B_HI, bl = B_LO; \ - asm("mtvsrd 0, %2\n\t" \ - "mtvsrd 1, %3\n\t" \ - "xxmrghd 0, 0, 1\n\t" \ - INSN " 0, 0\n\t" \ - "mfvsrd %0, 0\n\t" \ - "xxswapd 0, 0\n\t" \ - "mfvsrd %1, 0\n\t" \ + asm("mtvsrd 32, %2\n\t" \ + "mtvsrd 33, %3\n\t" \ + "xxmrghd 32, 32, 33\n\t" \ + INSN " 32, 32\n\t" \ + "mfvsrd %0, 32\n\t" \ + "xxswapd 32, 32\n\t" \ + "mfvsrd %1, 32\n\t" \ : "=r" (th), "=r" (tl) \ : "r" (bh), "r" (bl) \ - : "vs0", "vs1"); \ + : "v0", "v1"); \ printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \ "%016" PRIx64 "\n", bh, bl, th, tl); \ assert(th == T_HI && tl == T_LO); \ |