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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-02-24 01:35:43 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-01-06 23:07:06 +0000 |
| commit | 668ce343f6f54d9fe900a1884b876f8008908f4d (patch) | |
| tree | 21b554760492b117ca715b95f75b57f1cfdbfbe2 | |
| parent | 92c89a074cbcea660beb2259d9aa5b75f1490098 (diff) | |
| download | qemu-668ce343f6f54d9fe900a1884b876f8008908f4d.zip qemu-668ce343f6f54d9fe900a1884b876f8008908f4d.tar.gz qemu-668ce343f6f54d9fe900a1884b876f8008908f4d.tar.bz2 | |
tcg/s390x: Support MIE2 MGRK instruction
The MIE2 facility adds a 3-operand signed 64x64->128 multiply.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | tcg/s390x/tcg-target-con-set.h | 1 | ||||
| -rw-r--r-- | tcg/s390x/tcg-target.c.inc | 8 | ||||
| -rw-r--r-- | tcg/s390x/tcg-target.h | 2 |
3 files changed, 10 insertions, 1 deletions
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 33a82e3..b1a89a8 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -31,6 +31,7 @@ C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(o, m, 0, r) +C_O2_I2(o, m, r, r) C_O2_I3(o, m, 0, 1, r) C_O2_I4(r, r, 0, 1, rA, r) C_O2_I4(r, r, 0, 1, ri, r) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 9634126..871fcb7 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -175,6 +175,7 @@ typedef enum S390Opcode { RRE_SLBGR = 0xb989, RRE_XGR = 0xb982, + RRFa_MGRK = 0xb9ec, RRFa_MSRKC = 0xb9fd, RRFa_MSGRKC = 0xb9ed, RRFa_NRK = 0xb9f4, @@ -2319,6 +2320,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_debug_assert(args[0] == args[1] + 1); tcg_out_insn(s, RRE, MLGR, args[1], args[3]); break; + case INDEX_op_muls2_i64: + tcg_debug_assert((args[1] & 1) == 0); + tcg_debug_assert(args[0] == args[1] + 1); + tcg_out_insn(s, RRFa, MGRK, args[1], args[2], args[3]); + break; case INDEX_op_shl_i64: op = RSY_SLLG; @@ -3009,6 +3015,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_mulu2_i64: return C_O2_I2(o, m, 0, r); + case INDEX_op_muls2_i64: + return C_O2_I2(o, m, r, r); case INDEX_op_add2_i32: case INDEX_op_sub2_i32: diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 1fb7b8f..03ce11a 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -136,7 +136,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 1 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2) #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 |