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authorPaolo Bonzini <pbonzini@redhat.com>2025-03-21 14:17:52 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2025-03-21 19:34:36 +0100
commit64acc23c9793e86f2811345f3c122bf3ece8088b (patch)
treee0c39ff8e3dfdcdec1035fc8837f2f788aec4e1f
parentf7b87e464c8e9d30661fb9f519ed14fb053cd415 (diff)
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rust: hpet: fix decoding of timer registers
Due to a missing "& 0x18", timer registers are not decoded correctly. This breaks the tests/functional/test_x86_64_tuxrun.py functional test. Fixes: 519088b7cf6 ("rust: hpet: decode HPET registers into enums", 2025-03-06) Reported-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r--rust/hw/timer/hpet/src/hpet.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/rust/hw/timer/hpet/src/hpet.rs b/rust/hw/timer/hpet/src/hpet.rs
index 63c1971..3ae3ec2 100644
--- a/rust/hw/timer/hpet/src/hpet.rs
+++ b/rust/hw/timer/hpet/src/hpet.rs
@@ -776,7 +776,7 @@ impl HPETState {
let timer_id: usize = ((addr - 0x100) / 0x20) as usize;
if timer_id <= self.num_timers.get() {
// TODO: Add trace point - trace_hpet_ram_[read|write]_timer_id(timer_id)
- TimerRegister::try_from(addr)
+ TimerRegister::try_from(addr & 0x18)
.map(|reg| HPETRegister::Timer(&self.timers[timer_id], reg))
} else {
// TODO: Add trace point - trace_hpet_timer_id_out_of_range(timer_id)