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| author | Fabiano Rosas <farosas@linux.ibm.com> | 2022-01-28 13:15:03 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2022-01-28 13:15:03 +0100 |
| commit | 645d843ca55f0a7aa9be3ef19694d5a44b002f6e (patch) | |
| tree | 3a19bbb1fa3db0cb98bdb7d995bb94164b6f346b | |
| parent | 47822486f5e7d6dad8d9a2381d127a831a3c5c11 (diff) | |
| download | qemu-645d843ca55f0a7aa9be3ef19694d5a44b002f6e.zip qemu-645d843ca55f0a7aa9be3ef19694d5a44b002f6e.tar.gz qemu-645d843ca55f0a7aa9be3ef19694d5a44b002f6e.tar.bz2 | |
target/ppc: 405: Rename MSR_POW to MSR_WE
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | target/ppc/cpu.h | 1 | ||||
| -rw-r--r-- | target/ppc/cpu_init.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 2560b70..66e1307 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -327,6 +327,7 @@ typedef enum { #define MSR_S 22 /* Secure state */ #define MSR_KEY 19 /* key bit on 603e */ #define MSR_POW 18 /* Power management */ +#define MSR_WE 18 /* Wait State Enable on 405 */ #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ #define MSR_ILE 16 /* Interrupt little-endian mode */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e30e86f..e63705b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2535,7 +2535,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; - pcc->msr_mask = (1ull << MSR_POW) | + pcc->msr_mask = (1ull << MSR_WE) | (1ull << MSR_CE) | (1ull << MSR_EE) | (1ull << MSR_PR) | |