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| author | Pierrick Bouvier <pierrick.bouvier@linaro.org> | 2025-03-24 21:59:07 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-04-23 15:04:57 -0700 |
| commit | 63de8825af77edd71450f6bacaa55fb88d7f86e2 (patch) | |
| tree | 18e4c6fd052b5afbcaf179c5645bafccc9b5648b | |
| parent | 77b0893f60ecabdc796565d130343e50cfdf28f9 (diff) | |
| download | qemu-63de8825af77edd71450f6bacaa55fb88d7f86e2.zip qemu-63de8825af77edd71450f6bacaa55fb88d7f86e2.tar.gz qemu-63de8825af77edd71450f6bacaa55fb88d7f86e2.tar.bz2 | |
target/arm/cpu: remove inline stubs for aarch32 emulation
Directly condition associated calls in target/arm/helper.c for now.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250325045915.994760-23-pierrick.bouvier@linaro.org>
| -rw-r--r-- | target/arm/cpu.h | 8 | ||||
| -rw-r--r-- | target/arm/helper.c | 6 |
2 files changed, 6 insertions, 8 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b1c3e46..c1a0fae 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1222,7 +1222,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, */ void arm_emulate_firmware_reset(CPUState *cpustate, int target_el); -#ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); @@ -1254,13 +1253,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) #endif } -#else -static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } -static inline void aarch64_sve_change_el(CPUARMState *env, int o, - int n, bool a) -{ } -#endif - void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index becbbbd..7fb6e88 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6563,7 +6563,9 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, */ new_len = sve_vqm1_for_el(env, cur_el); if (new_len < old_len) { +#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); +#endif } } @@ -10628,7 +10630,9 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * Note that new_el can never be 0. If cur_el is 0, then * el0_a64 is is_a64(), else el0_a64 is ignored. */ +#ifdef TARGET_AARCH64 aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); +#endif } if (cur_el < new_el) { @@ -11640,7 +11644,9 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { +#ifdef TARGET_AARCH64 aarch64_sve_narrow_vq(env, new_len + 1); +#endif } } #endif |