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| author | Sairaj Kodilkar <sarunkod@amd.com> | 2025-02-07 10:23:53 +0530 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-02-21 07:18:42 -0500 |
| commit | 63dc0b8647391b372f3bb38ff1066f6b4a5e6ea1 (patch) | |
| tree | 2c8ba6899dc7296d0b24eb171167ed561ba3c563 | |
| parent | 1456e90653c46aceb3dd83a7b9889a32aad7700d (diff) | |
| download | qemu-63dc0b8647391b372f3bb38ff1066f6b4a5e6ea1.zip qemu-63dc0b8647391b372f3bb38ff1066f6b4a5e6ea1.tar.gz qemu-63dc0b8647391b372f3bb38ff1066f6b4a5e6ea1.tar.bz2 | |
amd_iommu: Use correct DTE field for interrupt passthrough
Interrupt passthrough is determine by the bits 191,190,187-184.
These bits are part of the 3rd quad word (i.e. index 2) in DTE. Hence
replace dte[3] by dte[2].
Fixes: b44159fe0 ("x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled")
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Message-Id: <20250207045354.27329-2-sarunkod@amd.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| -rw-r--r-- | hw/i386/amd_iommu.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 6b13ce8..98f1209 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1309,15 +1309,15 @@ static int amdvi_int_remap_msi(AMDVIState *iommu, ret = -AMDVI_IR_ERR; break; case AMDVI_IOAPIC_INT_TYPE_NMI: - pass = dte[3] & AMDVI_DEV_NMI_PASS_MASK; + pass = dte[2] & AMDVI_DEV_NMI_PASS_MASK; trace_amdvi_ir_delivery_mode("nmi"); break; case AMDVI_IOAPIC_INT_TYPE_INIT: - pass = dte[3] & AMDVI_DEV_INT_PASS_MASK; + pass = dte[2] & AMDVI_DEV_INT_PASS_MASK; trace_amdvi_ir_delivery_mode("init"); break; case AMDVI_IOAPIC_INT_TYPE_EINT: - pass = dte[3] & AMDVI_DEV_EINT_PASS_MASK; + pass = dte[2] & AMDVI_DEV_EINT_PASS_MASK; trace_amdvi_ir_delivery_mode("eint"); break; default: |