diff options
| author | Kele Huang <kele.hwang@gmail.com> | 2020-10-02 16:14:20 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-10-08 05:57:32 -0500 |
| commit | 62475e9d007d83db4d0a6ccebcda8914f392e9c9 (patch) | |
| tree | 8fc09c1a671e1213b930f8b4d97f02d212569bd5 | |
| parent | cae5d53b9e72d7a1e43cebeb36471d77a16c6e43 (diff) | |
| download | qemu-62475e9d007d83db4d0a6ccebcda8914f392e9c9.zip qemu-62475e9d007d83db4d0a6ccebcda8914f392e9c9.tar.gz qemu-62475e9d007d83db4d0a6ccebcda8914f392e9c9.tar.bz2 | |
accel/tcg: Fix computing of is_write for MIPS
Detect all MIPS store instructions in cpu_signal_handler for all available
MIPS versions, and set is_write if encountering such store instructions.
This fixed the error while dealing with self-modified code for MIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
[rth: Use uintptr_t for pc to fix n32 build error.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | accel/tcg/user-exec.c | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 5c96819..4ebe254 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -702,16 +702,51 @@ int cpu_signal_handler(int host_signum, void *pinfo, #elif defined(__mips__) +#if defined(__misp16) || defined(__mips_micromips) +#error "Unsupported encoding" +#endif + int cpu_signal_handler(int host_signum, void *pinfo, void *puc) { siginfo_t *info = pinfo; ucontext_t *uc = puc; - greg_t pc = uc->uc_mcontext.pc; - int is_write; + uintptr_t pc = uc->uc_mcontext.pc; + uint32_t insn = *(uint32_t *)pc; + int is_write = 0; + + /* Detect all store instructions at program counter. */ + switch((insn >> 26) & 077) { + case 050: /* SB */ + case 051: /* SH */ + case 052: /* SWL */ + case 053: /* SW */ + case 054: /* SDL */ + case 055: /* SDR */ + case 056: /* SWR */ + case 070: /* SC */ + case 071: /* SWC1 */ + case 074: /* SCD */ + case 075: /* SDC1 */ + case 077: /* SD */ +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 + case 072: /* SWC2 */ + case 076: /* SDC2 */ +#endif + is_write = 1; + break; + case 023: /* COP1X */ + /* Required in all versions of MIPS64 since + MIPS64r1 and subsequent versions of MIPS32r2. */ + switch (insn & 077) { + case 010: /* SWXC1 */ + case 011: /* SDXC1 */ + case 015: /* SUXC1 */ + is_write = 1; + } + break; + } - /* XXX: compute is_write */ - is_write = 0; return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } |