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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-02 07:15:18 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-06-02 07:15:18 +0000 |
| commit | 619dfca13a76da9bd10766858ed3ba40d4b303b2 (patch) | |
| tree | 61ac7ce13d51e37ac80eb1148224e69c1fb0285b | |
| parent | 091d055b3e6cab13ac3d6b151fcacdcfc059f03e (diff) | |
| download | qemu-619dfca13a76da9bd10766858ed3ba40d4b303b2.zip qemu-619dfca13a76da9bd10766858ed3ba40d4b303b2.tar.gz qemu-619dfca13a76da9bd10766858ed3ba40d4b303b2.tar.bz2 | |
Proper sign extensions for 32-bit divisions, spotted by Richard Sandiford.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4650 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-mips/translate.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 3ff7aec..e3481e4 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1900,6 +1900,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { int l1 = gen_new_label(); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1); { TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64); @@ -1912,6 +1914,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, tcg_gen_rem_i64(r_tmp2, r_tmp1, r_tmp2); tcg_gen_trunc_i64_tl(cpu_T[0], r_tmp3); tcg_gen_trunc_i64_tl(cpu_T[1], r_tmp2); + tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); + tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); gen_store_LO(cpu_T[0], 0); gen_store_HI(cpu_T[1], 0); } @@ -1923,6 +1927,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { int l1 = gen_new_label(); + tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1); { TCGv r_tmp1 = new_tmp(); @@ -1962,8 +1967,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { int l2 = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], 1ULL << 63, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1ULL, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[0], -1LL << 63, l2); + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_T[1], -1LL, l2); { tcg_gen_movi_tl(cpu_T[1], 0); gen_store_LO(cpu_T[0], 0); |