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| author | Matheus Ferst <matheus.ferst@eldorado.org.br> | 2021-12-17 17:57:13 +0100 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2021-12-17 17:57:13 +0100 |
| commit | 5f1470b091007f24035d6d33149df49a6dd61682 (patch) | |
| tree | 6b636ccdba4a212771ce3f2fd43e5f89b7e6e74b | |
| parent | 25ee608d79c1890c0f4e8c495ec8629d5712de45 (diff) | |
| download | qemu-5f1470b091007f24035d6d33149df49a6dd61682.zip qemu-5f1470b091007f24035d6d33149df49a6dd61682.tar.gz qemu-5f1470b091007f24035d6d33149df49a6dd61682.tar.bz2 | |
target/ppc: Implement Vector Expand Mask
Implement the following PowerISA v3.1 instructions:
vexpandbm: Vector Expand Byte Mask
vexpandhm: Vector Expand Halfword Mask
vexpandwm: Vector Expand Word Mask
vexpanddm: Vector Expand Doubleword Mask
vexpandqm: Vector Expand Quadword Mask
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | target/ppc/insn32.decode | 11 | ||||
| -rw-r--r-- | target/ppc/translate/vmx-impl.c.inc | 34 |
2 files changed, 45 insertions, 0 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e135b8a..9a28f1d 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -56,6 +56,9 @@ &VX_uim4 vrt uim vrb @VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4 +&VX_tb vrt vrb +@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb + &X rt ra rb @X ...... rt:5 ra:5 rb:5 .......... . &X @@ -408,6 +411,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN +## Vector Mask Manipulation Instructions + +VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb +VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb +VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb +VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb +VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb + # VSX Load/Store Instructions LXV 111101 ..... ..... ............ . 001 @DQ_TSX diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 8eb8d3a..ebb0484 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1491,6 +1491,40 @@ static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a) return true; } +static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb), + (8 << vece) - 1, 16, 16); + + return true; +} + +TRANS(VEXPANDBM, do_vexpand, MO_8) +TRANS(VEXPANDHM, do_vexpand, MO_16) +TRANS(VEXPANDWM, do_vexpand, MO_32) +TRANS(VEXPANDDM, do_vexpand, MO_64) + +static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + get_avr64(tmp, a->vrb, true); + tcg_gen_sari_i64(tmp, tmp, 63); + set_avr64(a->vrt, tmp, false); + set_avr64(a->vrt, tmp, true); + + tcg_temp_free_i64(tmp); + return true; +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \ |