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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-05-24 16:20:20 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2024-05-28 14:29:01 +0100 |
| commit | 5d874e5da23846c40dcb6d73a4c47bb95ff54372 (patch) | |
| tree | ebb72e68d0fb971e146860a85ffde7406b9ee3a5 | |
| parent | c0ca7ed049c468647e9e5239f4275565dcc39179 (diff) | |
| download | qemu-5d874e5da23846c40dcb6d73a4c47bb95ff54372.zip qemu-5d874e5da23846c40dcb6d73a4c47bb95ff54372.tar.gz qemu-5d874e5da23846c40dcb6d73a4c47bb95ff54372.tar.bz2 | |
target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16)
All of these insns have "if sz == '1' then UNDEFINED" in their pseudocode.
Fixes a RISU miscompare for invalid insn 0x5ef0c87a.
Fixes: 5c36d89567c ("arm/translate-a64: add all FP16 ops in simd_scalar_pairwise")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target/arm/tcg/translate-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5455ae3..0bdddb8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8006,7 +8006,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) case 0x2f: /* FMINP */ /* FP op, size[0] is 32 or 64 bit*/ if (!u) { - if (!dc_isar_feature(aa64_fp16, s)) { + if ((size & 1) || !dc_isar_feature(aa64_fp16, s)) { unallocated_encoding(s); return; } else { |