diff options
| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2024-08-28 10:36:51 +0200 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-02 15:11:51 +1000 |
| commit | 5b8764193be027b2298133a819358f636ff53962 (patch) | |
| tree | 51b67544c25446961b7c3d1c360b023bac68d5d4 | |
| parent | 55c136599f512a86e3fec9f77b6b5a30a6b34cca (diff) | |
| download | qemu-5b8764193be027b2298133a819358f636ff53962.zip qemu-5b8764193be027b2298133a819358f636ff53962.tar.gz qemu-5b8764193be027b2298133a819358f636ff53962.tar.bz2 | |
target: riscv: Add Svvptc extension support
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240828083651.203861-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu.c | 2 | ||||
| -rw-r--r-- | target/riscv/cpu_cfg.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 89bc395..658bdb4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -197,6 +197,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1494,6 +1495,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), + MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true), MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 96fe26d..355afed 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -81,6 +81,7 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_svvptc; bool ext_zdinx; bool ext_zaamo; bool ext_zacas; |