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authorBibo Mao <maobibo@loongson.cn>2025-06-18 10:51:34 +0800
committerBibo Mao <maobibo@loongson.cn>2025-07-11 14:47:15 +0800
commit5a2e76fc8786760a8fbb42af5cd8a61ecb6aba87 (patch)
tree5a97db42432b13f00f4e84bd82a5aeef87db6e43
parente5de64ae0233a13f5a623a62aec0b95d66ab7ce6 (diff)
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target/loongarch: Fix CSR STLBPS register write emulation
Function helper_csrwr_stlbps() is emulation with CSR STLBPS register write operation. However there is only parameter checking action, and no register updating action. Here update value of CSR_STLBPS when parameter passes to check. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn>
-rw-r--r--target/loongarch/tcg/csr_helper.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 46d331c..28b1bb8 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -29,7 +29,11 @@ target_ulong helper_csrwr_stlbps(CPULoongArchState *env, target_ulong val)
if (!check_ps(env, tlb_ps)) {
qemu_log_mask(LOG_GUEST_ERROR,
"Attempted set ps %d\n", tlb_ps);
+ } else {
+ /* Only update PS field, reserved bit keeps zero */
+ env->CSR_STLBPS = FIELD_DP64(old_v, CSR_STLBPS, PS, tlb_ps);
}
+
return old_v;
}