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| author | Cédric Le Goater <clg@kaod.org> | 2019-01-29 11:46:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-01-29 11:46:05 +0000 |
| commit | 597d6bb3e8a93c4c0670df93f07c321ae84d2930 (patch) | |
| tree | 9805fce96bf95bc0eab98c975b2a18f939890152 | |
| parent | b617ca9223353624000017e2fa499d6d3296b293 (diff) | |
| download | qemu-597d6bb3e8a93c4c0670df93f07c321ae84d2930.zip qemu-597d6bb3e8a93c4c0670df93f07c321ae84d2930.tar.gz qemu-597d6bb3e8a93c4c0670df93f07c321ae84d2930.tar.bz2 | |
aspeed/smc: define registers for all possible CS
The model should expose one control register per possible CS. When
testing the validity of the register number in the read operation,
replace 's->num_cs' by 'ctrl->max_slaves' which represents the maximum
number of flash devices a controller can handle.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-id: 20190124140519.13838-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/ssi/aspeed_smc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 7af808c..6045ca1 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -665,7 +665,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == s->r_ce_ctrl || addr == R_INTR_CTRL || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) { + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { return s->regs[addr]; } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |