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authorFea.Wang <fea.wang@sifive.com>2024-12-03 11:49:27 +0800
committerAlistair Francis <alistair.francis@wdc.com>2024-12-20 11:22:47 +1000
commit59018ec72f4bbc8bc291006899847dbf66a65255 (patch)
treebf806918e2327cda2f5b73aaa5de222562e5837f
parent1a65064c1f4dc701370c1d59ac1b85afa198b3b0 (diff)
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target/riscv: Add svukte extension capability variable
Refer to the draft of svukte extension from: https://github.com/riscv/riscv-isa-manual/pull/1564 Svukte provides a means to make user-mode accesses to supervisor memory raise page faults in constant time, mitigating attacks that attempt to discover the supervisor software's address-space layout. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241203034932.25185-2-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r--target/riscv/cpu_cfg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc4..d8771ca 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;