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| author | TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> | 2024-09-19 13:50:45 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:07 +1000 |
| commit | 58597bfeab45be303a4e514ce375e56b1b0c627e (patch) | |
| tree | 98fbabbe3990819b1ea5bb3344ba416c76ef9f69 | |
| parent | 870589dcddcc542d88c5f0cdd9b2b43becc8a070 (diff) | |
| download | qemu-58597bfeab45be303a4e514ce375e56b1b0c627e.zip qemu-58597bfeab45be303a4e514ce375e56b1b0c627e.tar.gz qemu-58597bfeab45be303a4e514ce375e56b1b0c627e.tar.bz2 | |
target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240919055048.562-6-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/cpu_helper.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 621bf4c..203c0a9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1677,6 +1677,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong tinst = 0; target_ulong htval = 0; target_ulong mtval2 = 0; + int sxlen = 0; + int mxlen = 0; if (!async) { /* set tval to badaddr for traps with address information */ @@ -1805,7 +1807,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_SPP, env->priv); s = set_field(s, MSTATUS_SIE, 0); env->mstatus = s; - env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1)); + sxlen = 16 << riscv_cpu_sxl(env); + env->scause = cause | ((target_ulong)async << (sxlen - 1)); env->sepc = env->pc; env->stval = tval; env->htval = htval; @@ -1836,7 +1839,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) s = set_field(s, MSTATUS_MPP, env->priv); s = set_field(s, MSTATUS_MIE, 0); env->mstatus = s; - env->mcause = cause | ~(((target_ulong)-1) >> async); + mxlen = 16 << riscv_cpu_mxl(env); + env->mcause = cause | ((target_ulong)async << (mxlen - 1)); env->mepc = env->pc; env->mtval = tval; env->mtval2 = mtval2; |